In recent years, portable communication terminals represented by cellular phones are widely used. Such portable terminals are generally driven by batteries and it is strongly desired to reduce power consumption without sacrificing operation speed in portable terminals in order to prolong the lifetime of batteries. To achieve a portable communication terminal with low power consumption without reducing operation speed, it is effective to increase drain saturation current to maintain current driveability while lowering threshold voltage to reduce supply voltage in the portable terminal. To satisfy such demands, there have been many studies on heterojunction MOS transistors (which will be hereinafter called “hetero MOS”) using as a channel region a material with high-mobility carriers.
In a known MOS transistor, carriers travel along the interface between a gate oxide film and a silicon substrate. Energy level largely fluctuates around the interface between the gate oxide film that is an amorphous layer and the silicon substrate that is a crystal layer. Because of the energy level fluctuation, carriers are easily affected by interface scattering in the known MOS transistor, resulting in problems such as reduction of carrier mobility and increase in noise.
On the other hand, in the hetero MOS, which is a MOS transistor including a semiconductor heterojunction for a channel region, a semiconductor heterojunction interface is formed at a depth with a small distance apart from the gate insulating film of a semiconductor substrate. A channel is formed at the semiconductor heterojunction interface and carriers travel along the channel. The semiconductor heterojunction interface is an interface where crystal layers are joined together, and thus energy level at the interface does not fluctuate widely. Therefore, the influence of interface scattering on carriers is small. Accordingly, the hetero MOS has a great current driveability and an excellent characteristic of reduction in noise. Furthermore, the hetero MOS has another characteristic that its threshold voltage can be lower than that of the known MOS transistor.
Problems to be Solved
However, in the hetero MOS including a heterojunction for a channel region, the channel region is embedded and therefore threshold voltage largely depends on the thickness of an Si cap region.
FIG. 15 illustrates the structure of a known hetero MOS.
As shown in FIG. 15, the known hetero MOS 100 includes an Si substrate 101, a gate insulating film 102 formed on the Si substrate 101, a gate electrode 103 which is formed of polysilicon containing a p-type impurity of high concentration on the gate insulating film 102, and a sidewall spacer 104 which is formed on the gate insulating film 102 to cover side faces of the gate electrode 103. The Si substrate 101 includes p-type source and drain regions 105 and 106 which are formed on both sides of the gate electrode, an n-type Si cap region 107 formed in a region located between the source and drain regions 105 and 106, an n-type SiGe channel region 108 formed under the Si cap region, 107 an n-type Si buffer region 109 formed under the SiGe channel region 108, and an n-type Si body region 110 formed under the Si buffer region 109.
FIG. 16 shows the results obtained from simulations of dependency of threshold voltage on the thickness of the Si cap region 107 in the known hetero MOS 100.
As shown in FIG. 16, as the thickness of the Si cap region 107 is increased, the absolute value for its threshold voltage remarkably increases. In other words, the threshold voltage is remarkably increased. This is because as the position at which the channel is formed (i.e., the interface between the Si cap region 107 and the SiGe channel region 108) is located a more distance apart from the gate electrode, i.e., further in depth, the potential at the channel changes less enough according to the gate voltage.
In terms of processing, however, the thickness of the Si cap region 107 is reduced through fabrication processes such as an SiO2 thermal oxide film formation process and a cleaning process, and thus it is very difficult to control the thickness of the Si cap region 107. Therefore, nonuniformity in the thickness of the Si cap region 107 can be easily caused. Accordingly, variation in threshold voltage is easily caused and therefore there may be cases where a desired operation can not be performed because of increased threshold voltage.
Particularly, in an integrated circuit including a plural number of identical transistors, variation in threshold voltage among the transistors causes gaps of switching time among the transistors. As a result, the timing gaps among the transistors in the integrated circuit occur, so that the integrated circuit may not operate properly. Moreover, under consideration of variation in threshold voltage among the transistors, in order to ensure an operation margin, the latest switching timing should be set as a standard timing and therefore it is difficult to increase in operation speed of the integrated circuit.